The present invention relates generally to electronic circuit testing, and more specifically, to multi-cycle signal identification for static timing analysis.
Static timing analysis is used in circuit design to determine a maximum achievable frequency of a circuit. Static timing analysis is oriented around the concept of a cycle, which is a repetitive pattern in time during which a unit of information is conveyed in the circuit. The length of a cycle is determined based on standard latch-to-latch launch capture patterns in a circuit design. Cycle-based analysis may be extended to support complex circuit topologies and signaling methods used in large high-frequency structures such as memory arrays. Differentiation of signal types drives variations in checking, propagation, and analysis for various types of circuit elements, such as clocks (timing only information), static logic (level-sensitive, sampled values), and domino logic (pulse based logic).
If signals do not obey assumptions of signal classification within the circuit's cycle, then the signals cannot be treated appropriately by static timing analysis. Therefore, for a circuit comprising multi-cycle logic, static timing analysis may not be effectively applied. For example, correct recognition of gating versus merging of signals, handling of domino circuits, or generated clocks may not be possible. A particular class of multi-cycle logic is controlled by the use of local clocks that are logic-generated. The logic-generated clocks retain the synchronous nature of the timing paths, rather than depending on precise delays to ensure correct selection of multiple co-existing edges in cones of logic. The logic-generated clocks are common in high performance environments (such as microprocessor logic) as well as high efficiency environments (such as memory structures where density and power are more important than single-cycle response times).